Intel 430MX PCIset Timing Specification

Solution:

• Intel 430MX PCIset Timing Specification Datasheet Addendum

  The information in this document is provided as a supplement to the standard package datasheets published for the Intel 430MX PCIset. Please refer to the standard package datasheets (order numbers 290524 for MTSC and MTDP, and 290525 for MPIIX) for product information and specifications not found in this document.
  
  NOTICE: This document contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design.

• Intel 82437MX and 82438MX Datasheet (Intel 430MX PCISET)

  The Intel 430MX PCIset consists of the 82437MX System Controller (MTSC), two 82438MX Data Paths (MTDP), and the 82371MX PCI I/O IDE Xcelerator (MPIIX). The PCIset forms a Host-to-PCI bridge and provides the second level cache control and a full function 64-bit data path to main memory. The MTSC integrates the cache and main memory DRAM control functions and provides bus control for transfers between the CPU, cache, main memory, and the PCI Bus. The second level (L2) cache controller supports a write-back cache policy for cache sizes of 256 Kbytes and 512 Kbytes. Cacheless designs are also supported. The cache memory can be implemented with either standard, burst, or pipelined burst SRAMs. An external Tag RAM is used for the address tag and an internal Tag RAM for the cache line status bits. For the MTSC DRAM controller, four rows are supported for up to 128 Mbytes of main memory. The MTSC optimized PCI interface allows the CPU to sustain the highest possible bandwidth to the graphics frame buffer at all frequencies. Using the snoop ahead feature, the MTSC allows PCI masters to achieve full PCI bandwidth. The MTDPs provide the data paths between the CPU/cache, main memory, and PCI. For increased system performance, the MTDPs contain read prefetch and posted write buffers.